A semiconductor integrated circuit (IC) has a large number of electronic components, such as transistors, logic gates, diodes, wires, etc., that are fabricated by forming layers of different materials and of different geometric shapes on various regions of a silicon wafer. The design of an integrated circuit transforms a circuit description into a geometric description called a layout. The process of converting specifications of an integrated circuit into a layout is called the physical design.
Chip designers often use electronic design automation (EDA) software tools to assist in the design process. Chip design using EDA software tools generally involves an iterative process whereby the chip design is gradually perfected. A top-down design methodology is commonly employed using hardware description languages (HDLs), such as Verilog or VHDL for example, by which the designer creates an integrated circuit by hierarchically defining functional components of the circuit, and then decomposing each component into smaller and smaller components.
The various components of an integrated circuit are initially defined by their functional operations and relevant inputs and outputs. From the HDL or other high level description, the actual logic cell implementation is typically determined by logic synthesis, which converts the functional description of the circuit into a specific circuit implementation. The logic cells are then “placed” (e.g., given specific coordinate locations in the circuit layout) and “routed” (e.g., wired or connected together according to the designer's circuit definitions). The placement and routing software routines generally accept as their input a flattened netlist that has been generated by the logic synthesis process. This flattened netlist identifies the specific logic cell instances from a target standard cell library, and describes the specific cell-to-cell connectivity. In the area of custom designs, where complexity is less than digital design, the ‘logic synthesis’ approach is not taken, and the user can instead directly conduct placement and routing based on the logic connection blueprint (schematic). In addition, with respect to custom designs, users may hand-craft their own proprietary library of components, rather than using standard-cell library, just for better optimization.
Conventionally, routing is accomplished either using an automated process or a manual process. Automatic or assisted placement and routing are commonly used to facilitate the design process and gain advantage on fast turn-around time from design to manufacturing, and then to final products. This automated approach provides the advantage of allowing the electronic design to be routed in a comprehensive way with minimal direct design by the user. The disadvantage of the automated approach is that it does not allow for fine-granularity control over specific routing actions for specific portions of the design.
A manual approach allows a user to manually configure specific portions of the electronic design with a high degree of control over the final design product. A manual approach may include the following sequence of actions using a wire editor: (a) user manually determines which net(s) belong to certain the area in which routing is intended; (b) user selects a specific net to create wire(s) with connectivity; (c) the wire is created manually in a location selected by the user; (d) connections are formed to pins, which involves insertion of vias if the pins are on different layers of the design; (e) a determination is made whether more wires are needed in the are under design, where if the answer is “Yes”, then the process loops back to step “b”; (f) if the answer for step “e” is “No”, then additional actions are now taken to adjust spacing between wires and vias to address any design rule violations; and (g) a further determination is made whether placement of instances needs to be changed to resolve design rule issues, where if so, the process loops back to step “b”.
While the manual allows the user to have a high level of control over the design activity for specific portions of the design, the problem is that many of the steps in the manual process is very time-consuming and requires a great deal of expertise and domain knowledge from the user to be implemented correctly. The manual approach therefore leads to lower levels of productivity from designers/engineers. On the other hand, while the automated approach provides higher levels of productivity, automated routing leads to loss of control over individualized design decisions for specific portions of the design.
Therefore, there is a need for an improved approach to implement routing that that can provided detailed levels of control for routing of specific portions of an electronic design, while still maintaining the productivity gains associated with automated routing.